In certain types of computing systems that include a central processing unit (CPU) and a host bridge or what is known as a “Northbridge,” such devices are connected by an interface using a particular protocol in order for the CPU and Northbridge to communicate. One such protocol known in the art is HyperTransport™, which provides a high speed, point-to-point link for interconnecting integrated circuits within a computing system. Typically, however, Northbridge circuits communicate with other devices in the system, such as input-output bridges (e.g., a “Southbridge”) according to different protocols, including PCI Express. Accordingly, when a CPU is trying to communicate with a Southbridge via the Northbridge and the CPU communicates with the Northbridge via HyperTransport™ protocol and the Northbridge, in turn, communicates with the Southbridge via PCI Express protocol, not all message types or formats are easily passed through the Northbridge to communicate the commands or requests from the CPU to the Southbridge.
Types of messages in HyperTransport™ protocol that do not easily pass through the Northbridge, as an example, are what are termed “Broadcast” messages, which simply provide a memory address, but no data field in order to communicate different and various commands to the Southbridge. This is problematic in some types of Northbridges that are configured to communicate commands via PCI Express to the Southbridge using a different packet construction including a data field, for example. Thus, it becomes necessary to convert these Broadcast messages of HyperTransport™, as an example, to a format usable and recognizable by the communication link between the Northbridge and Southbridge in order to ensure simplification of the system, as well as avoiding, for example, further connections of the interface between the Northbridge and Southbridge such as using a different communication link to accommodate the non-compatible messages.
It is noted that the following documents are known in the art concerning HyperTransport™ technology and PCI and their functioning. The following documents are incorporated herein by reference:    1) “HyperTransport™ I/O Link Specification, Revision 1.05c”; Document #HTC2002104-0005-0005; Aug. 5, 2003; HyperTransport Technology Consortium.    2) “HyperTransport™ I/O Link Errata, Revision 1.05b”; Document #HTC200335-0024-0003; Apr. 2, 2003, HyperTransport Technology Consortium.    3) “Advanced Configuration and Power Interface Specification, Revision 2.0b;” Oct. 11, 2002; Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, Phoenix Technologies Ltd., and Toshiba Corporation.    4) “AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Data Sheet;” 24888 Rev 3.03—Jul. 12, 2004; Advanced Micro Devices, Inc.    5) “Clock Generator Specification for AMD64 Processors;” Publication # 24707 Revision: 3.08; September 2003; Advanced Micro Devices, Inc.    6) “HyperTransport™ Technology I/O Link—A High-Bandwidth I/O Architecture;” Jul. 20, 2001; Advanced Micro Devices, Inc.